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Digital Systems and Hardware Description Languages

Code: 102684 ECTS Credits: 9
Degree Type Year Semester
2500895 Electronic Engineering for Telecommunication OB 2 1
2500898 Telecommunication Systems Engineering OB 2 1
The proposed teaching and assessment methodology that appear in the guide may be subject to changes as a result of the restrictions to face-to-face class attendance imposed by the health authorities.


Mercedes Rullán Ayza

Use of Languages

Principal working language:
catalan (cat)
Some groups entirely in English:
Some groups entirely in Catalan:
Some groups entirely in Spanish:

Other comments on languages

És possible que el grup en català sigui el 411


Josep Velasco González
Lluís Antoni Teres Teres


There are no prerequisites. However, it is recommended for students to have previously taken the courses “Fundamentals of Computing” and “Theory of Circuis and Electronics”.

Objectives and Contextualisation

This is a basic training course, taught during the second academic year, first semester.  Is the bridge between the courses “Theory of Circuits and Electronics” and “Fundamentals of Computing”, in the first year, and “Computer Architecture and Peripherals”, in the second year. 

The objectives of this course are for students to understand the role of digital systems in the computer world, be capable of designing low-to-medium complexity digital systems using logic gates and reconfigurable devices, and understand that a computer is simply a digital system of a certain complexity. In the last part of the course, a simple computer open source (RISC-V) is presented in order for the students to understand the concepts of process-unit, control-unit, instruction set, microinstructions, microorders and microprogramming.


    Electronic Engineering for Telecommunication
  • Develop personal work habits.
  • Develop thinking habits.
  • Learn new methods and technologies, building on basic technological knowledge, to be able to adapt to new situations.
  • Work in a team.
    Telecommunication Systems Engineering
  • Develop personal work habits.
  • Develop thinking habits.
  • Learn new methods and technologies, building on basic technological knowledge, to be able to adapt to new situations.
  • Work in a team.

Learning Outcomes

  1. Analyse and design combinational and sequential, synchronous and asynchronous, microprocessor and integrated circuits.
  2. Apply the basics of hardware device description languages.
  3. Develop applications in real time.
  4. Develop critical thinking and reasoning.
  5. Develop independent learning strategies.
  6. Develop systemic thinking.
  7. Develop the capacity for analysis and synthesis.
  8. Manage available time and resources.
  9. Manage available time and resources. Work in an organised manner.
  10. Use computer tools to research bibliographic resources or information on telecommunications and electronics.
  11. Use the basics of software design, verification and validation in the description of hardware systems based on high level hardware description languages.
  12. Work cooperatively.


Block 1: Combinational Circuits (CC)

  • Digital signals and digital systems. Description of digital systems. Electronic digital systems (EDS). MOS transistors. AND, OR and INV logical gates. Synthesis of EDS as a process of successive refinements.
  • Combinational Circuits. Synthesis from a table I: ROM. Synthesis from a table II: logic gates.
  • Boolean algebra. Truth tables.
  • NAND, NOR, XOR, NXOR logical gates. 3-state buffers.
  • Features: Propagation time. Cost
  • Other combinational blocks: multiplexers, decoders, AND-OR planes (PLAs).
  • Synthesis tools: Synthesis from algorithms.

Block 2: Sequential Circuits (SC)

  • The need for sequential circuits. Some examples. States and synchronization. Synchronous sequential circuits. Clock, reset and set.
  • Explicit functional description of SCs. State transition graphs and tables.
  • Basic components: Flip flops and latches.
  • Synthesis of SC from tables. Moore and Mealy machines. States encoding.
  • Registers, counters and memories. Structures, types and most common uses.
  • Finite state machines (FSM). Formal definition. Implementation. Propagation times.
  • Hardware description language: VHDL. Some examples of FSM description using VHDL.
  • Sequential implementation of algorithms.
  • Physical implementation of digital circuits. Field Programmable Gate Arrays (FPGA) and other implementation strategies.

Block 3: Process Unit-Control Unit (PU-CU) architecture and processors

  • PU-CU architecture.
  • PU with multiplexers. PU with busses.
  • ROM based Control Unit with sequencers.
  • Basic structure of a microprocessor. Von Neumann architecture vs Harvard. Functional units and busses.
  • Processor instruction set. Programming with machine language. Micro-orders and status signals.
  • Example of open sourceprocessor: RISC-V
  • Harvard architecture. Fetch, decoding and execution cycles.
  • Microinstructions and microprograms.
  • Microprogrammed implementation of the Control Unit.
  • Relations between pure hardware, firmware, and high-level software languages.


The subject is organized in three blocks. Blocks 1 and 2 use a Coursera free access MOOC developed by the teachers of the subject. The materials offered through the MOOC include a series of videos that students must view before attending class and that contain the theoretical-practical knowledge needed for the design of digital systems, interactive self-correction exercises and a simulation environment. of digital systems. Block 3 materials include a series of videos that are available through the UAB virtual campus. Block 3 uses the same work methodology indicated in the previous paragraph, without the Coursera environment.

The subject is taught in "classroom problems" mode. All face-to-face classes are treated as problem-based sessions. The classes are dedicated to solving questions and doubts in the videos, and cases proposed by the teacher. Students must actively participate in these classes; these are not conventional "theory" classes. They take place in small groups (of the order of 40-50 students), an indispensable condition to reach the necessary degree of interactivity in a subject of eminently practical character.

Previous activities are complemented by laboratory practice where students design and simulate different parts of a simple processor which is finally  implemented on a FPGA. To physically implement the circuits, a design environment for programmable logic devices (INTEL-ALTERA) is used. Students will become familiar with the concepts of schematic capture, functional simulation, temporal simulation, and the description of complex digital systems using hardware description languages (VHDL).

Depending on the evolution of the health situation that are established, the practices could be carried out partially or completely in a non-contact mode.

Tutoring sessions may be individual or in small groups and will be done on demand and in coordination between each teacher and the related students. There may also be open tutoring sessions for all interested students that may be proposed by the teaching staff; but these will require prior submission to the corresponding forum of the Virtual Campus (CV) those specific questions about concepts or exercises that must be addressed in order for the teachers to plan and carry out that tutoring properly.

The following transversal skills are addressed and assessed during the course:

T01.01 - Develop critical thinking and reasoning. T01.02 - Develop the capacity for analysis and synthesis. T01.04 - Develop systemic thinking. They are worked on in the face to face classes and assessed within the partial tests.

T02.02 - Develop independent learning strategies. T02.03 - Manage available time and resources. Work in an organised manner. Students must develop these skills by taking responsibility for viewing the videos before classes and doing the exercises autonomously. The viewing (and understanding) of the videosis assessed through questionnaires Moodle at the beginning of the classes. Both the questionnaires and the problems delivered are part of the final grade.

T03.01 - Work cooperatively. This skill is addressed and assessed in the laboratory practices, where students must work in groups of two.

Annotation: Within the schedule set by the centre or degree programme, 15 minutes of one class will be reserved for students to evaluate their lecturers and their courses or modules through questionnaires.


Title Hours ECTS Learning Outcomes
Type: Directed      
Exercise-based classes 18 0.72 1, 6, 5, 7, 4, 9, 12
Face to face classes 26 1.04 1, 2, 7, 4, 10, 11
Laboratory practices 18 0.72 2, 5, 9, 12, 11
Type: Supervised      
Case study 18 0.72 5, 4, 9
Laboratory practice assignments 10 0.4 2, 6, 5, 7, 4, 8, 9, 12, 11
Type: Autonomous      
Autonomous work 39 1.56 5, 8, 9
Preparing and solving exercises 32 1.28 1, 2, 10, 11
Preparing laboratory sessions 30 1.2 9, 12
Videos viewing 18 0.72 5, 7, 4, 8, 9


a) Assessment activities

For partial or final assessment tests, the teaching staff can decide on any combination of the following modalities:

  1. Objective test, face-to-face or virtual, to evaluate the fundamental conceptual knowledge of the subject. This test could be part of a two-phase exam and be eliminatory, so that if this part is not passed, the second part can no longer be taken or will not be evaluated.
  2. Exercise resolution test where students will have to apply the knowledge acquired to solve any exercise that can be addressed with the contents taught and regardless of whether or not identical or similar examples have been performed in class.
  3. Combined test between basic conceptual knowledge and applied exercises; that is, a combined test of the two above.

All tests and exams may be with or without notes and face-to-face or virtual depending on the circumstances. This all remains at the discretion of the teaching staff, who must announce it well in advance and, if possible, at the beginning of the classes in each block associated with a partial or final exam.

Student assessment includes the following activities:

  1. Three individual partial tests (one test per block), carried out individually, face-to-face, in a controlled environment, and in written format. These partial tests assess the student's acquired knowledge and his/her capability to design efficient digital circuits and systems.
  2. Exercises resolution: a set of on-line exercises, with automatic grading, must be delivered on previously scheduled dates.
  3. Webinars attendance, and the viewing of videos before attending the class will be assessed through eventual “5-minutes tests” that will be carried out within the webinar itself.
  4. For each laboratory session, the attendance (in-class or online as determined), the lab-work preparation and the work carried out during the session will be assessed. Let’snote that, depending on the circumstances, and if deemed appropriate, it may be necessary to schedule a practical exam to complete the assessment.

b) Assessment procedure

The mark of the course by continued assessment (CA) is obtained from:

  1. (activity 1) The mark obtained in the 3 partial tests (PT1PT2PT3),
  2. (activities 2 and 3) the delivery of exercises, answer to questionnaires and class attendance (Pb),
  3. (activity 4) the mark of the laboratory activities (LT), and

according to the formula: CA = PT · 0.5 + LT · 0.3 + Pb · 0.2

where PT = (PT1+PT2+PT3)/3

To pass the course the following conditions must be met:

  1. CA ≥ 5
  2. PT1PT2, and PT3 must be ≥ 4, and PT must be ≥5, and
  3. LT must be ≥ 5

 At the end of the course:

  • If the mark obtained in PT1PT2, or PT3 (only one of them) is < 4, the student is encouraged to raise this mark by repeating the test scored under 4. To pass the course, the new mark obtained must be ≥ 4, and the new average of the three marks must be ≥ 5. The mark PT will be this new average.
  • If a student has obtained a mark < 4 in two or more partial tests, he is encouraged to take a final test of the whole course curriculum. The mark PT will be the grade obtained in this test, which must be ≥ 5 to pass the course.

If PT < 5 or LT < 5 after retaking these new tests, the final score of the course will be the lowest number between CA and 4.5.

The following figure summarizes the possible situations for students having passed the laboratory practices (that is, LT≥ 5)




 c) Assessment activities: scheduling

Dates of the assessment tests and the submission of exercises are published in the Virtual Campus (VC) and may be subject to changes in programming due to unforeseen eventualities. Any modification will be reported through this platform.

It is important to bear in mind that no assessment activities will be permitted for any student at a different date or time to that established, unless for justified causes duly advised before the activity and with the lecturer’s previous consent. In all other cases, if an activity has not been carried out, this cannot be re-assessed.

d) Grades review

Grades obtained by students in each test are published in the VC. Once the grades arepublished, students will be informed of the procedure to follow to review their exam. Students must request, through the VC, an exam review, and will receive a call with the day and time to do it through TEAMS.

Any student who does not follow this procedure, within the time frame established, may not request a new review.

e) Irregularities committed by the student, copy and plagiarism

Notwithstanding other disciplinary measures deemed appropriate, and in accordance with the academic regulations in force, assessment activities will receive a zero whenever a student commits academic irregularities that may alter such assessment. Assessment activities graded in this way and by this procedure will not be re-assessable. If passing the assessment activity or activities in question is required to pass the subject, the awarding of a zero for disciplinary measures will also entail a direct fail for the subject, with no opportunity to re-assess this in the same academic year.

Irregularities contemplated in this procedure include, among others:

  • the total or partial copying of a test, practical exercise, report, or any other evaluation activity;
  • allowing others to copy;
  • presenting group work that has not been done entirely by the members of the group;
  • presenting any materials prepared by a third part as one’s own work, even if these materials are translations or adaptations, including work that is not original or exclusively that of the student;
  • having communication devices such as mobile phones, smart watches, etc., accessible during theoretical-practical in-class assessment tests (individual exams).

f) Assessment of students who followed the subject last year but do not successfully passed it

Except for those who had committed some of the irregularities cited in the previous section, students who completed and passed the laboratory practices in the previous course but did not pass the course, may choose not to repeat them again during the current academic year. In that case, the laboratory practices grade (LT) will be 5, regardless of the grade reached the previous year.

The list of students who can choose this option will be published at the beginning of the course in the VC. If, anyway, the student wants to make the laboratory practices again, he/she must communicate it by mail to the course Coordinator.

If a student has committed irregularities (copies/plagiarism) in any evaluation activity in a previous call of the subject he will not have the right to have his practices validated (if he had approved them).

g) Special grades

  • A "non-assessable" grade cannot be assigned to students who have participated in any of the individual partial tests or the final test.
  • In order to reach the qualification “with Honours”, the final grade must be ≥ 9.0. Because the number of students with this distinction cannot exceed 5% of the number of students enrolled in the course, this distinction will be awarded to whoever has the highest final grade.

To consult the academic regulations approved by the Governing Council of the UAB, please follow this link: https://www.uab.cat/doc/TR_Normativa_Academica_Plans_Nous


Assessment Activities

Title Weighting Hours ECTS Learning Outcomes
3 partial test and/or final test 50% 8 0.32 1, 2, 6, 5, 7, 4, 8, 9, 10, 11
Exercises delivering 20% 8 0.32 5, 7, 4, 8, 9
Laboratory practices 30% 0 0 1, 2, 3, 7, 4, 8, 9, 12, 11


  • Coursera MOOC: https://www.coursera.org/learn/digital-systems
  • Digital Systems: From Logic Gates to Processors. Deschamps JP, Valderrama E, Terés L. Springer 2017. ISBN 978-3-319-41198-9.
  • Complex Digital Systems. Deschamps JP, Valderrama E, and Terés L. Springer 2019. ISBN 978-3-030-12652-0.
  • Diseño de Sistemas Digitales. Deschamps JP, Ed. Paraninfo 1989. ISBN 84-283-1695-9 (in spanish).
  • Digital Systems Fundamentals. T.L. Floyd. Ed. Prentice Hall. 9ª Edición ISBN: 8483220857.
  • Desenvolupament del microprocessador LittleProc: des de la primera porta lògica fins a una plataforma reconfigurable. J. Saiz, A.Portero, R. Aragonès. Materials 234.  Servei de Publicacions de la UAB; ISBN (paper format): 978-84-490-2700-0, ISBN (e-book): 978-84-490-2699-7 (in catalan. Book used for the preparation of the laboratory sessions).


In the laboratory session we will use the software Altera Quartus II 9.0 WebEdition. Students will be required to install this software, which does not require any license.