Degree | Type | Year |
---|---|---|
4313797 Telecommunication Engineering | OB | 1 |
You can view this information at the end of this document.
Knowledge on the following subjects is recommented:
Digital Signal Processing
Electronic Systems Design
Digital Sistemes and Hardware Description Languages
Electronic Systems and Applications
(This course has been updated for the year 2024-25)
The main objective of this course is to learn, understand and be able to design electronic systems for digital signal processing with the focus on integrated systems. These Systems are composed of integrated circuits that manage their computation and communication. The study of these integrated systems will be oriented to the usual digital signal processing architectures with the focus on applications of acoustics, audio and speech processing.
Different design methodologies will be used according to the level of abstraction (system, architecture, implementations). Hardware Description Languages (HDL) will be introduced. In order to implement such systems in the labs you will use electronic boards with FPGA reconfigurable devices.
1. Introduction to Integrated System Design for Digital Processing
Fundamentals of Digital Signal Processing (Quantization, Sampling, Z-transform, Filer design, Digital Fourier Transform)
Microelectronic Design Methodologies for ASIC and FPGA
2. High-level Digital Signal Processing
Introduction to Acoustics and Spatial Audio
Introduction to Speech Sounds and Speech Processing
Source Filter Models
Speech Coding
Perceptual Models and Hearing Devices (Hearing Aids and Cochlear Implants)
Speech Enhancement and Source Separation Algorithms
Spatial Audio (Introduction to Vector Based Amplitude Panning and Ambisonics)
3. Adaptation for Implementation of Signal Processing Algorithms
Asynchronous sample rate conversion (ASRC)
Real time low latency processing (circular buffers)
Optimization of algorithms (Fast Fourier Transform – Radix algorithms)
Floating point to Fixed Point conversion Algorithms
Platforms and libraries for audio and hearing aid real time processing
4. Deployment on Integrated Systems
Integrated circuits structure: FPGAs
HDL Modelling, simulation and synthesis
Clock and Power Management
Verification and prototyping
Laboratories: Real-time Audio and Speech Digital Signal Processing on FPGA
Title | Hours | ECTS | Learning Outcomes |
---|---|---|---|
Type: Directed | |||
Laboratory Sessions | 15 | 0.6 | 1, 2, 4, 5, 6, 7, 8, 9, 10 |
Lectures | 30 | 1.2 | 1, 3, 4, 5, 6, 7, 8, 10 |
Type: Supervised | |||
Thematic Homework (Individual) | 10 | 0.4 | 1, 6, 7, 8, 9 |
Type: Autonomous | |||
Laboratory activities preparation and reporting | 20 | 0.8 | 1, 2, 4, 5, 7, 8, 10 |
Study | 69 | 2.76 | 1, 3, 4, 5, 6, 7, 8, 10 |
The course will be mainly driven by the lectures, that will use adhoc material (presentations, documents, links, tools and other resources) available in the virtual campus (VC) of the UAB.
Students will deliver exercices on specific subjects (on the Virtual Campus).
Laboratory work will let the students to apply and experiment the concepts acquired on FPGA platforms widelly used in industry.
Annotation: Within the schedule set by the centre or degree programme, 15 minutes of one class will be reserved for students to evaluate their lecturers and their courses or modules through questionnaires.
Title | Weighting | Hours | ECTS | Learning Outcomes |
---|---|---|---|---|
Inidividual Exercises | 15% | 1 | 0.04 | 1, 6, 7, 8, 9 |
Laboratory work reports | 35% | 1 | 0.04 | 1, 2, 4, 5, 6, 7, 8, 9, 10 |
Partial Evaluación (Part 1): Exam | 25% | 2 | 0.08 | 3, 4, 5, 7, 8, 9, 10 |
Partial Evaluación (Part 2): Exam | 25% | 2 | 0.08 | 1, 3, 6, 9 |
Student assessment uses continuous evaluation made up of the following assessments:
• Two partial exams for the each part of the course, which gives 25% of the final grade.
• Individual work in thematic exercises (delivered on the virtual campus), which accounts for 15% of the final grade
• Team work in the laboratory, scheduled in 5 sessions, with the obligation to deliver the corresponding individual reports. An evaluation above 5 is mandatory to pass the course. This activity contributes 35% to the final grade of the course.
The final exam allows students to assess the achievement of skills in a single exam or to recover any partial assessments that had a mark lower than 3.5. That is also the minimum mark requered for any of the parts to pass the course and the average mark of both exams is not below 5.
A weighted final grade of not lower than 5 is required to pass the course.
In order to obtain MH, students will need to have an overall qualification higher than 8.5 with the limitations of the UAB (1 MH/10 students). As a reference criterion, they will be assigned in descending order.
Plagiarism will not be tolerated either in exams or in individual activities on the Virtual Campus. In this case, the available tools will be used to verify it. All students involved in plagiarism will be automatically suspended. A final grade of no more than 30% will be assigned.
The student will receive a grade of "Not Evaluable" if:
- the student has not been able to be evaluated in the laboratory due to not attendance or not deliver the corresponding reports without justified cause.
- the student has not carried out a minimum of 50% of the activities proposed.
- the student has not taken the final exam.
Repeating students will be able to “save” their grade in lab but not in the rest of the activities.
Digital Speech Processing
Acoustics and 3D Audio
Psychoacoustics
Hearing Aids and Cochlear Implants
Integrated and Embedded Systems:
The electronic design tools (EDA) associated with Intel-Altera FPGA boards used in laboratories that enable:
- Specification of digital systems in HDL languages
- Building SoC architectures for RISC processors (ARM, NIOS)
- Logical and physical synthesis of HDL
- Downloading HW and SW code from the PC to the FPGA
- Execution of the algorithm in the FPGA
Intel Altera's DE1_SoC board will be used as the SoC-FPGA platform.
Students will have free access, upon request, to courses on industrial EDA tools (CADENCE) useful for their curriculum and training, mainly for subjects 3 and 4.
https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/training/learning-maps.pdf
Information on the teaching languages can be checked on the CONTENTS section of the guide.