Degree | Type | Year | Semester |
---|---|---|---|
2500895 Electronic Engineering for Telecommunication | OT | 4 | 0 |
The following backgrund is advised:
The overall goal of this syllabus is double:
Chapter 1. Introduction to the design of analog integrated circuits
1.1. From the Idea to the Chip
1.2. Microelectronic vs Electronic Design
1.3. CMOS Technologies
1.4. Device Modeling
1.5. The Operational Amplifier and its FoMs
1.6. Lab Proposal: My OpAmp in CNM 2.5um CMOS Technology (CNM25)
Chapter 2. Single Stage OpAmps
2.1. The Mono-Transistor Amplifier
2.2. Differential Topologies
2.3. Common Mode Feedback
2.4. Folded Amplifiers
2.5. Cascode Topologies
2.6. Gain Enhancement Techniques
Chapter 3. Multi-Stage OpAmps
3.1. Two-Stage Topologies
3.2. Miller Effect
3.3. Frequency Compensation
3.4. Design Space
Introduction to the CNM25 APDK (http://www.cnm.es/~pserra/apdk)
Chapter 4. Full-Custom Analog Design Methodology
4.1. Device Sizing
4.2. Process and Mismatching Simulation
4.3. The Art of Analog Layout
4.4. Physical Verification
4.5. Parasitics Extraction
4.6. DFM Techniques
Chapter 5. Low-Power OpAmps
5.1. Low-Voltage vs Low-Current
5.2. Subthreshold Operation
5.3. Class-AB Output Stages
5.4. Rail-to-Rail Topologies
5.5. Inverted-Based Pseudo-Differential Multi-Stage Architectures
Chapter 6. OpAmp Application Examples
6.1. Pre-Amplification
6.2. MRC-Amplifiers for AGC
6.3. Continuous-Time Gm-C Filters
6.4. Switched-Capacitor Filters
Chapter 7. Integrated Data Converters
7.1. ADC vs DAC
7.2. Flash Architectures
7.3. SAR Topologies
7.4. Integrating Solutions
7.5. Delta-Sigma Modulators
Title | Hours | ECTS | Learning Outcomes |
---|---|---|---|
Type: Directed | |||
Case studies and exercises | 12 | 0.48 | 2, 6, 3 |
Lab sessions | 12 | 0.48 | 2, 3, 9, 12, 13 |
Lectures | 26 | 1.04 | 2, 6, 3 |
Type: Supervised | |||
Tutorials | 12 | 0.48 | 2, 6, 5, 3 |
Type: Autonomous | |||
Lab pre-work | 8 | 0.32 | 1, 2, 6, 5, 3, 7, 10, 8, 9, 12, 13 |
Study | 68 | 2.72 | 11, 2, 6, 5, 4, 3 |
progressive evaluation of the overall mark is based on the following weights:
Lab work (including sessions and report) is mandatory to pass evaluation. The above evaluation scheme is only applicable when individual marks are greater or equal to 3/10. Otherwise, students must take de remedial exam.
In case the student applies for the remedial exam, its weight will be 50% of the overall mark, together with the lab report (40%) and solved exercises (10%).
Any student not compliant with the above criterias will be considered "Non Evaluable",
Any change on the above evaluation method will be communicated in advance to the affected students.
Title | Weighting | Hours | ECTS | Learning Outcomes |
---|---|---|---|---|
Individual work | 50% | 4 | 0.16 | 11, 1, 2, 6, 5, 3, 7, 10, 8, 9, 12 |
Lab report | 40% | 4 | 0.16 | 1, 2, 6, 4, 3, 9, 12, 13 |
Remedial exam | 50% | 2 | 0.08 | 2, 6, 3, 9 |
Solved exercises | 10% | 2 | 0.08 | 2, 6, 5, 3, 9 |
Teachin materials supplied during lecture sessions are almost self-explanatory. For a deeper understanding of both theoretical and practical contents, the following readings are recommended:
P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Oxford University Press, http://www.aicdesign.org
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Education
F. Maloberti, Analog Design for CMOS VLSI Systems, Kluwer Academic Publishers
T. Tuma and A. Burmen, Circuit Simulation with SPICE OPUS: Theory and Practice, Modeling and Simulation Science,
Engineering andTechnology, Birkhäuser Boston
A. Hastings, The Art of Analog Layout, Pearson Prentice Hall