Degree | Type | Year | Semester |
---|---|---|---|
4313797 Telecommunications Engineering | OB | 1 | 2 |
Knowledge on the following subjects is recommented:
Electronic Systems Design
Digital Sistemes and Hardware Description Languages
Electronic Systems and Applications
The main objective of this course is to learn, understand and be able to design electronic systems with the focus on embedded systems. These Systems are composed of integrated circuits (or SoC from Systems on a chip) that manage their capacity of computation and communication through wired or wireless protocols. The study of these integrated systems will be oriented to the usual digital processing archtiectures in modern electronics: single-core (i.e. wireless sensor networks), multi-core (i.e. multimedia devices) and many core (high performance computing), and the different types of computation: data-flow and reactive. Digital systems are integrating also non digital components such as sensors, actuators, analog, RF and power components. We will review the different fabrication technologies available in the market, from silicon technologies to new processes for organic and flexible electronics, and we will use FPGA platforms to implement such systems in the labs.
1. Introduction to the Design of Integrated Systems for Digital Processing
Fundamental Concepts bàsics on Ciber-Phyísical Systems
Functional Specificacions
User Centered Design
Performmance Requirements
Technologies for the Fabrication of Integrated Circuits
2. Integrated Circuit Design Methodologies
ASIC and FPGA Design Methodologies
VHDL Modelling, simulation and synthesis
High Level System Design
3. Integrated Systems Implementation Technologies
Digital CMOS cell libraries
EDA Tools
Industrialization; IPs and Patents
Printed Electronics and High Performance PCBs
4. Systems-on-a-Chip Design
Computational Models and Advanced Programming
SoC and MPSoC Architectures
Embedded Plataforms
Verification, Prototyping and Test
Laboratory: Integrated Digital Processing on FPGA
The course will be mainly driven by the lectures, that will use adhoc material (presentations and documents) available in the virtual campus of the UAB.
Two seminars are schedulled and others can also be added, according to the parallel activity at UAB, in order to analyse in depth specific topics.
Laboratory work will let the students to apply and experiment the concepts acquired on FPGA platforms widelly used in industry.
According to the personal interests of every student, a scientific and/or technologic paper will be selected in order to get familiar and evaluate the knowledge that is available through specialized journals and publications.
Optionally, for students with previous knowledge in embedded systems and/or VHDL and/or FPGA we are proposing their participation in international challenges for embedded systems. That participation will replace the activities of laboratory and critical review.
Title | Hours | ECTS | Learning Outcomes |
---|---|---|---|
Type: Directed | |||
Laboratory Sessions | 15 | 0.6 | 1, 2, 5, 4, 6, 7, 8, 9, 10 |
Lectures | 22 | 0.88 | 1, 5, 3, 4, 6, 7, 8, 10 |
Thematic Seminars | 4 | 0.16 | 1, 3, 6, 7, 8, 9 |
Type: Supervised | |||
Selection and follow-up of a personalized scientific-technologic journal paper | 14 | 0.56 | 1, 6, 7, 8, 9 |
Type: Autonomous | |||
Laboratory activities preparation and evaluation | 20 | 0.8 | 1, 2, 5, 4, 7, 8, 10 |
Study | 69 | 2.76 | 1, 5, 3, 4, 6, 7, 8, 10 |
The evaluation of the course will follow the rules of the continuous evaluation and the final grade for the course, is calculated with the proportions on the above table that contains:
• 2 parcial exams containign both theoretical concepts and exercices. Minimum mark on those exams is 3 (over 10)
• Team work at lab scheduled in 5 sessions with the need to deliver the corresponding reports (delivered individually). This is mandatory to pass the course evaluation.
• Individual work on the critical review of a specific scientific and/or technological paper
• The optionalparticipation in an international challenges from embedded systems companies will replace the activities of laboratory and critical review.
To obtain MH it will be necessary that the students have an overall qualification higher than 8.5 with the limitations of the UAB (1MH /
10students). As a reference criterion they will be assigned in descending order.
A final weighted average mark not lower than 50% is sufficient to pass the course, provided that a score over one third of the range is attained
in everyone of the 3 marks.
Plagiarism will not be tolerated. All students involved in a plagiarism activity will be failed automatically. A final mark no higher than 30% will be
assigned.
An student not having achieved a sufficient final weighted average mark, may opt to apply for remedial activities the subject under the following
conditions:
- the student must have participated in the problem-based learning laboratory activities, and
- the student must have a final weighted average higher than 30%, and
- the student must not have failed any activity due to plagiarism.
The student will receive a grade of "Not Evaluable" if:
- the student has not been able to be evaluated in the laboratory and learning-based activities due to not attendance or not deliver the
corresponding reports without justified cause.
- the student has notcarried out a minimum of 50%of the activities proposed in tutored sessions.
- the student has not taken the final exam
Repeating students will be able to “save” their grade in lab and problem-based learning activities but not in the rest of the activities.
Title | Weighting | Hours | ECTS | Learning Outcomes |
---|---|---|---|---|
1st Parcial Test | 25% | 2 | 0.08 | 5, 3, 4, 7, 8, 10 |
2nd Parcial Test | 25% | 2 | 0.08 | 5, 3, 4, 7, 8, 10 |
Critical review of a personalized scientific-Technologic paper | 15% | 1 | 0.04 | 1, 6, 7, 8, 9 |
Laboratory work reports | 35% | 1 | 0.04 | 2, 5, 4, 6, 7, 8, 9, 10 |
F. Balarin et al.: “Hardware-Software Co-Design of Embedded Systems: The POLIS Approach”
Rajsuman, Rochit ."System-on-a-Chip: Design and Test"
P. Bricaud, M. Keating : “Reuse Methodology Manual for System-On-A-Chip Designs”
L. Terés, Y. Torroja, S. Olcoz, E. Villar: “VHDL: Lenguaje estándar de diseño electrónico”
I. Grout “Digital Systems Design with FPGAs and CPLDs”
H.J.M. Veendrick “Nanometer CMOS: from ASICS to BASICS”, 2ª edición, Springer. 2017.
http://www.europractice.com/
Example of international challenge http://www.innovatefpga.com/portal/