Degree | Type | Year | Semester |
---|---|---|---|
2500895 Electronic Engineering for Telecommunication | OT | 4 | 0 |
To face this subject in the best conditions it is convenient to have a previous knowledge of circuit resolution, equivalent models of large and small signal and general knowledge of elecctronic, both analog and digital.
To have a general view of the microelectronic design problem.
To know the stages of the design of an integrated circuit, distinguishing those that correspond specifically to the designer and those that correspond to the technologist.
To know the strategies and design stages, together with the CAD tools used, as well as the different alternatives or design styles.
To understand the operation of general-purpose analog and digital circuits.
UNIT 1. Introduction to microelectronic design
1.1 Evolution of microelectronics
1.2 Basic concepts of microelectronic design
1.3 Design flow
UNIT 2. Fundamentals of the MOS transistor in microelectronic design
2.1 MOSFET Physical structure
2.2 MOSFET Model
2.3 CMOS design parameters
2.4 CMOS technological scaling
2.5 Design of passive elements: resistors, capacitors
UNIT 3: Analog microelectronic design
3.1 Active resistors
3.2 Current sources. Current mirrors.
3.3 Basic inverting amplifiers. Cascode configuration.
3.4 Differential stage.
3.5 The operational amplifier
UNIT 4. Digital microelectronic design
4.1 MOSFET model for digital design
4.2 The inverter: DC characteristic, commutation characteristic and layout
4.3 Full custom design of CMOS gates
During the semester, theory lessons and exercises will be held in the classroom. Theory lessons will present the scientific-technical knowledge of the subject in a structured, clear and ordered manner. The students will learn the basics with instructions on how to complete and deepen these contents. During the exercises, in small groups, students will have to solve problems related to the subject exposed in the master classes, with the teacher's support. The objective is to complete and deepen the understanding of the contents of the subject.
A total of 4 sessions of laboratory sessions, of compulsory attendance will be planned. The objective of the lab sessions is to promote active student learning by working on the implementation and design of basic digital circuits, as well as developing critical reasoning and teamwork competencies. Some of the practice sessions could be done at home, based on health alerts
Title | Hours | ECTS | Learning Outcomes |
---|---|---|---|
Type: Directed | |||
problems | 12 | 0.48 | 5, 6 |
theory classes | 24 | 0.96 | 2, 1, 5, 3 |
Type: Supervised | |||
problem solving assisted by the teacher's tutelage | 12 | 0.48 | 5, 3 |
Type: Autonomous | |||
Individual study | 52 | 2.08 | 2, 1, 4, 3 |
Problem solving | 20 | 0.8 | 4, 5, 3, 6 |
Report on practical work (lab work) | 12 | 0.48 | 5, 6 |
Search of information | 12 | 0.48 | 5, 7, 6, 8 |
Continuous evaluation process:
The evaluation of the subject will be carried out continuously through two types of clearly differentiated activities: lab sessions and homework
1. Lab sessions:
The attendance to the lab sessions and the delivery of the corresponding reports are indispensable condition to pass the subject.
A minimum score of 5 is required to be considered for the evaluation of the subject. A mark smaller than 5 in the lab sessions implies the student wlll fail the complete subject.
Students who have completed the course 2018-2019 and have passed the lab sessions, can validate the note.
2. Works proposed by the teacher:
Two written reports and / or oral presentation will be proposed by the teacher , corresponding to an analog and digital design respectivaly. The work must be done individually.
Students who have failed some of the works must submit to a final synthesis exam and examine all the material not approved. A minimum final mark of 5 points will be required to make average with the rest of the marks obtained by the student
Recovery process: final exam
The final synthesis exam will consist of two parts, corresponding to each half of the subject. In order to be evaluated, the student must have a lab mark equal to or greater than 5 and must have previously delivered the corresponding analog design activity.
Students can also attend to the final exam, even if they have passed, to improve the final qualification. In these cases the students renounce to the previous mark. A final minimum mark of 4 points will be required in the synthesis test to be computed with the rest of the marks.
In accordance with the current academic regulations, irregularities committed by a student that can lead to a variation of the qualification will be evaluated with a zero (0). For example, plagiarizing or copying an evaluation activity, will imply a zero mark in the activity. Assessment activities qualified in this way will not be recoverable. If it is necessary to pass any of these assessment activities, the student will fail this subject, without opportunity to recover it in the same course.
The proposed teaching and evaluation methodologies may be subjected to modification, depending on possible restrictions imposed by the health authorities on face-to-face attendance.
Special qualifications
Only if the student does not present the lab report ofor homework, the note will be Non-Valuable. Otherwise, the final qualification will be calculated based on the weight of each evaluation activity.
For each subject , the number of Honors qualifications results from calculating the five percent or fraction of the students enrolled inall the teaching groups. Students will only be awarded if they have obtained a final mark equal to or greater than 9.00, and whenever the teacher considers it appropriate(depending on the student's excellence).
Title | Weighting | Hours | ECTS | Learning Outcomes |
---|---|---|---|---|
Report on practical work (lab work) | 35% | 2 | 0.08 | 2, 1, 4 |
Specific written and/or oral presentation of a digital design | 25% | 1 | 0.04 | 2, 1, 4, 5, 3, 7, 6, 8 |
Specific written and/or oral presentation of an analog design | 40% | 3 | 0.12 | 2, 1, 4, 5, 3, 7, 6, 8 |